CDA4101, Assignment 1

Due Thursday 2/18

1. A high-speed 8088 might have acheived 1 MIPS. An earlier Core i7 might have acheived 100,000 MIPS. Refer to Instructions Per Second for a discussion on MIPS.
   • Assume that an ISA level instrcution on the 8088 is interpreted to 3 instructions at the hardware level, on average.
   • Assume that an ISA level instrcution on the Core i7 is interpreted to 5 instructions at the hardware level, on average.

   The Core i7 can simulate the 8088 instruction set. Assume that each ISA level instruction from the 8088 can be interpreted to 2 ISA level instructions on the Core i7.

   1. How many milliseconds would it take to run 1,000,000 8088-ISA level instructions on this 8088?
   2. How many milliseconds would it take to run 1,000,000 8088-ISA level instructions on this Core i7?
   3. The 8088 was a dedicated machine for its ISA. The Core i7 can interpret the 8088 ISA. Is a hardware implementation always faster than a software implementation?
2. Identify the computer:
   1. First Intel computer with a single, five-stage pipeline
   2. First Intel computer with a dual, five-stage pipeline
   3. First Intel computer with a superscalar pipeline
   4. First product line developed as a family.
   5. Computer that marked the start of modern computer history.
   6. First vector computer.
   7. First commercial RISC machine
   8. First computer with a bus for I/O
   9. First dual-core chip.
3. Consider a student record with name, age, and major number. The name is Pat Adams, the age is 19, the major number is 2022. Show how the data would be stored in a memory system that has 4-byte words as follows. Draw the memory as a linear array, not as a table. Store numbers in hex.
   1. Store the data using Big Endian
   2. Store the data using Little Endian
4. Prove whether or not these equations are equivalent by using truth tables. Do not simplify the expressions.
   • A OR B
   • (A OR B)C OR (A OR B)(NOT C)
5. Consider the three input boolean function that is a 1 if the binary equivalent of the inputs is 0, 2, 3, 6, 7.
   • Draw a circuit diagram for this function using only 2-input NOR gates.
   • Draw a circuit diagram for this function using the MSI multiplexer chip in the Multiplexers section of the book. Do not draw the inside of the multiplexer.
6. A 2-bit encoder is a circuit with four input lines, exactly one of which is high at every instant, and two output lines whose 2-bit binary value tells which input is high. Only one of the input lines will ever be active at the same time. You do not have to consider the cases if more than one is active.
   1. Draw the truth table for a 2-bit encoder. There will be four input variables and two output variables. Only one of the input variables can be 1 at a given time, so there are only 4 possible combinations for valid input variables.
   2. Draw the circuit for the 2-bit encoder.
   3. Draw the circuit for a 3-bit encoder. There will be 8 input lines and 3 output lines.
      
7. A 2-bit demultiplexer is a circuit with one input line, two control lines and four output lines. The input line will appear on one of the output lines based on the control lines. Draw the circuit for a 2-bit demultiplexer.
8. The shifter from the book only has two functions: logical shift right and logical shift left. Create a new circuit that implements a 4-bit shifter with four functions: arithmetic shift right, don't shift, logical shift left, logical shift right. The shifting done in the book is logical shifting: a 0 is placed into the S0 or S7 bit, depending on which way the shift goes. An arithmetic shift right places D0 into both S0 and S1: it is duplicating the sign bit. A don't shift operation would send each data bit to the corresponding output: D0 to S0, D1 to S1, etc. Be sure that only one of these functions is enabled at a time.
9. The book shows how to create an adder from two half-adders. A subtractor can be created in a similar fashion.
   1. Draw the truth table for a half-subtractor.
   2. Draw the circuit for a half-subtractor.
   3. Draw the truth table for a full subtractor.
   4. Draw the circuit for a full subtractor.
10. List all 6 control signals for the ALU to generate the following. Do not use any question marks.
    1. A OR B
    2. The constant 1
    3. The constant -1
    4. B - A
11. Draw the SR latch using NAND gates instead of NOR gates. Label all input and output lines.
12. Answer these questions about this circuit diagram.
    1. In terms of the input values for clock and data,
       1. when will Latch A be in a nondeterministic state (both input lines are 1)?
       2. when will Latch B be in a nondeterministic state?
       3. when does Latch C change its state?
       4. if Output 1 is 0, when does it change to 1?
       5. if Output 2 is 0, when does it change to 1?
    2. In ten words or less, what is this circuit?

    

    I have created a running example of this circuit using digital works. Download digital works and my example to run it

13. On many CPUs there are condition codes to test if the answer was zero, and to test if there was signed overflow: Z and O. An 8-bit ALU is constructed from 8 1-bit ALUs in Fig. 3-19. How would each of these condition codes be wired to such an ALU? Draw the circuits for each. (The O bit is set when the carry into the highest ALU is different from the carry out of the highest ALU). Fig. 3-19 is difficult to read. Please refer to my lecture when I explained the diagram.
14. 14. Calculate the bus bandwidth to display 1280x1024 full-color video at 30 frames/sec. Assume that the data must pass over the bus twice, once from the CD-ROM to the memory and once from the memory to the screen.
15. 15. The new FIU-PCI Express system has 10 Gbps lanes (gross capacity), in one direction. How many signal wires (not including ground) are needed in one direction for x32 operation? What is the gross capacity for x32 operation, one way (GBps)? What is the net capacity one way, assuming 8/10b? What would be the net capacity if 128/130b is used?

14. Bus Speed
    • DDR3 runs at 166.67MHz. How many nanoseconds are in one cycle?
    • A cycle is 4 nanoseconds. How many cycles are in one second?
15. Memory Chips
    • What is the maximum number of addresses for a chip that has 12 address lines, 3 bank lines, RAS and CAS?
    • What is the number address lines that are used for CAS in a 1Mx8 chip that has 18 10 address lines, 2 bank lines, RAS and CAS? Assume that RAS uses all available address lines.
16. The 4 X 3 memory of Figure 3-28 uses 22 AND gates and three OR gates. It also has 11 input, output, and control lines.
    1. Suppose the circuit were expanded to 64 x 16.
       1. How many AND gates would be needed?
       2. How many OR gates would be needed?
       3. How many pins would be coming into and out of the chip?
    2. Suppose the circuit were expanded to 16 x 64.
       1. How many AND gates would be needed?
       2. How many OR gates would be needed?
       3. How many pins would be coming into and out of the chip?
          
17. Refer to the timing diagram of Fig. 3-38. The time needed from the point where !MREQ is asserted and the data must be stable before it is read can be calculated two ways from the table.
    1. Calculate the time needed using both calculations for a 100MHz bus.
    2. If the memory needs 15 nsec for this measurement, how many wait states are needed to read from the memory on a 100MHz bus?
    3. Calculate the time needed using both calculations for a 200MHz bus.
    4. If the memory needs 15 nsec for this measurement, how many wait states are needed to read from the memory on a 200MHz bus?
18. Refer to Figure 3-46. The precharge phase cannot be issued until two full cycles after the last READ or WRITE operation. The ACTIVATE command must precede the first READ or WRITE to the same bank by two cycles. Data is produced in the next cycle after a READ. Using the maximum amount of (legal) pipelining,
    1. how many bus cycles are needed to read a word from four different rows of bank 0, including the final precharge?
    2. how many bus cycles are needed to read two words from the same row in bank 0 and two words from the same row in bank 1, including the final precharges?
    3. how many bus cycles are needed to read one word from each of the four banks, including the final precharges?

Quiz

The quiz for this assignment will be on Tuesday, February 23. We will review the solution to this assignment in class on Thursday, February 18.